1. Field of the Invention
The present invention generally relates to high speed data transmission and, more particularly to encoding data for high speed synchronous data transmission.
2. Background Description
As computer performance and computer peripheral performance improve, computer to computer and computer to peripheral communications become more complicated. In the fall of 1995, the IEEE adopted the 1394 High Speed Serial Bus standard, which defines operating points at 100 MegaHertz (MHZ), 200 MHz and 400 MHz. The IEEE 1394 standard is rapidly being accepted as the standard for high speed data communications.
To achieve high speed data transmission at these rates, data is transmitted non-return-to-zero (NRZ) and the transmission clock is encoded into a second NRZ serial signal, STROBE. STROBE is defined by: EQU STROBE.sub.new =DATA.sub.new .sym.DATA.sub.old .sym.STROBE.sub.old ,
wherein the subscript "old" indicates the current value of DATA or STROBE and "new" indicates the next, subsequent value. This encoding scheme is known as the Manchester encoding scheme.
Using the Manchester encoding scheme STROBE and Data are transmitted, serially, and the transmission clock is extracted at the receiving end from STROBE and DATA.
FIG. 1 is a schematic diagram provided in the IEEE 1394 specification of a prior art circuit 100 for generating STROBE and DATA. The circuit includes two edge triggered D-type latches 102, 104 and two exclusive ORs (EXORs) 106, 108. DATA.sub.old is latched in latch 102 and STROBE.sub.old is latched in latch 104. DATA.sub.new is provided to EXOR 106 and the D input to latch 102. DATA.sub.new is EXORed with DATA.sub.old in EXOR 104 and the result is provided to EXOR 108. The result from EXOR 106 is then EXORed with STROBE.sub.old to generate the D input (STROBE.sub.new) to latch 104. On each rising clock edge, the values of DATA.sub.new and STROBE.sub.new are latched into latches 102 and 104 as DATA.sub.old and STROBE.sub.old with a new value for DATA.sub.new being supplied.
While this circuit is adequate for generating STROBE at 100 MHz or 200 MHz, logic delays inherent in current logic families make a 400 MHz STROBE difficult to implement. Further, controlling STROBE and DATA transmission requires complicated control logic. Thus, there is a need for a circuit for generating STROBE at a 400 MHz data rate that is less sensitive to logic delays.